CMOS Imager Design in Cadence

April 2022
EN.520.216 Introduction to VLSI

Objectives:

Use Cadence to design a CMOS imager chip

Write a final report in IEEE format

Skills Applied & Outcomes:

Cadence schematic, layout, and simulations

Layout Vs. Schematic (LVS), Design Rule Check (DLC)

Comments:

I sketching and designing layouts on paper and in the software, debugging, and writing the report. We made a few mistakes at the beginning but managed to fix them by the end of the project.